When designing an integrated circuit, an automated process may be utilized. Typically, a floor planner is utilized to lay out an integrated circuit wherein a floor planner is a tool for automatically placing logic components, memory components and other circuit elements on the integrated circuit as is well known. The results obtained from the floor planning tool may then be utilized by a logic synthesizer to better predict the functionality and performance of the integrated circuit design.
However, at least one problem with such a design of integrated circuits is that data available to a logic synthesizer for estimating timing delays within the integrated circuit are design general and not design specific. For example, look-up tables are typically used to estimate various timing delays wherein such look up tables are generated from average effects experienced across an entire integrated circuit (IC) family. However, an entire IC family may range in size from a few thousand gates to hundreds of thousands of gates. As a result, the look up tables are very general and assumptions about linearity, variability, accuracy, and granularity adversely affect the specific design results in most cases.
Hence, there is a need for a method and tool that can provide more accurate timing delay information that relates specifically to design conditions of the target integrated circuit. Moreover, it would be advantageous to incorporate this tool into a floor planning tool thereby providing a method of correlating the floor planning and synthesis results with respect to placement and routing delays within the integrated circuit.